[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"article-5-risc-v-basics-for-builders-en":3,"article-related-5-risc-v-basics-for-builders-en":33,"series-industry-342f03ea-5b21-4fdb-8bcb-ae75c6be3a2a":82},{"id":4,"slug":5,"title":6,"content":7,"summary":8,"source":9,"source_url":10,"author":11,"image_url":12,"cover_image":12,"category":13,"language":14,"translated_content":11,"related_article_id":15,"keywords":16,"key_takeaways":25,"views":29,"created_at":30,"published_at":31,"topic_cluster_id":32},"342f03ea-5b21-4fdb-8bcb-ae75c6be3a2a","5-risc-v-basics-for-builders-en","5 RISC-V basics for builders","\u003Cp data-speakable=\"summary\">\u003Ca href=\"\u002Ftag\u002Frisc-v\">RISC-V\u003C\u002Fa> is an open instruction set architecture used from microcontrollers to servers.\u003C\u002Fp>\u003Cp>RISC-V is an open CPU instruction set architecture that now powers chips from tiny embedded parts to server-class designs. It was introduced in 2014, and RISC-V International now has more than 4,500 members, which shows how fast the ecosystem has grown.\u003C\u002Fp>\u003Ctable>\u003Cthead>\u003Ctr>\u003Cth>Item\u003C\u002Fth>\u003Cth>What it is\u003C\u002Fth>\u003Cth>Notable detail\u003C\u002Fth>\u003C\u002Ftr>\u003C\u002Fthead>\u003Ctbody>\u003Ctr>\u003Ctd>RISC-V base ISA\u003C\u002Ftd>\u003Ctd>Open instruction set architecture\u003C\u002Ftd>\u003Ctd>Royalty-free and license-friendly\u003C\u002Ftd>\u003C\u002Ftr>\u003Ctr>\u003Ctd>Standard extensions\u003C\u002Ftd>\u003Ctd>Optional capability blocks\u003C\u002Ftd>\u003Ctd>M, A, F, D, Q, C, B, V\u003C\u002Ftd>\u003C\u002Ftr>\u003Ctr>\u003Ctd>Register sets\u003C\u002Ftd>\u003Ctd>Core architecture resources\u003C\u002Ftd>\u003Ctd>16 or 32 general-purpose registers\u003C\u002Ftd>\u003C\u002Ftr>\u003Ctr>\u003Ctd>Bit widths\u003C\u002Ftd>\u003Ctd>Supported implementations\u003C\u002Ftd>\u003Ctd>32, 64, and 128 bits\u003C\u002Ftd>\u003C\u002Ftr>\u003C\u002Ftbody>\u003C\u002Ftable>\u003Ch2>1. The open ISA model\u003C\u002Fh2>\u003Cp>RISC-V is not a single chip or a single company product. It is a specification for how software talks to hardware, and that makes it useful for groups that want control over their own processor design. Because the spec is open and royalty-free, teams can build compatible cores without paying per-unit fees.\u003C\u002Fp>\n\u003Cfigure class=\"my-6\">\u003Cimg src=\"https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779361569517-1iaf.png\" alt=\"5 RISC-V basics for builders\" class=\"rounded-xl w-full\" loading=\"lazy\" \u002F>\u003C\u002Ffigure>\n\u003Cp>That matters for both research and shipping products. The architecture was developed at the University of California, Berkeley, and later maintained by RISC-V International, which moved to Switzerland in 2019 and became a Swiss nonprofit business association in 2020.\u003C\u002Fp>\u003Cul>\u003Cli>Open specification, not a vendor lock-in program\u003C\u002Fli>\u003Cli>Compatible implementations can be open source or proprietary\u003C\u002Fli>\u003Cli>Works for academic projects and commercial silicon\u003C\u002Fli>\u003C\u002Ful>\u003Ch2>2. The base design choices\u003C\u002Fh2>\u003Cp>RISC-V follows reduced instruction set computer principles. It uses a load-store design, variable instruction encoding, and little-endian byte order in common implementations. The core idea is to keep the base simple, then add only the features a design really needs.\u003C\u002Fp>\u003Cp>That simplicity is one reason it fits so many targets. The ISA supports 32-bit, 64-bit, and 128-bit variants, and it defines a small set of general-purpose registers with optional floating-point and vector registers.\u003C\u002Fp>\u003Cul>\u003Cli>Load-store architecture\u003C\u002Fli>\u003Cli>Variable encoding, including compressed 16-bit instructions\u003C\u002Fli>\u003Cli>General-purpose registers: 16 or 32, depending on the profile\u003C\u002Fli>\u003C\u002Ful>\u003Ch2>3. The standard extension set\u003C\u002Fh2>\u003Cp>RISC-V gets much of its flexibility from extensions. The base ISA can be expanded with modules for multiplication, atomics, floating point, compressed code, bit manipulation, and vectors. That lets a microcontroller stay small while a performance chip can add the features needed for heavier workloads.\u003C\u002Fp>\n\u003Cfigure class=\"my-6\">\u003Cimg src=\"https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779361570717-3tlv.png\" alt=\"5 RISC-V basics for builders\" class=\"rounded-xl w-full\" loading=\"lazy\" \u002F>\u003C\u002Ffigure>\n\u003Cp>The extension model also helps software teams plan for different classes of hardware. A compiler or operating system can target a specific profile, while silicon vendors choose the mix that fits power, area, and speed goals.\u003C\u002Fp>\u003Ccode>Common extensions: M, A, F, D, Q, C, B, V\u003Cbr>Control support: Zicsr\u003Cbr>Fence support: Zifencei\u003C\u002Fcode>\u003Ch2>4. The range of implementations\u003C\u002Fh2>\u003Cp>RISC-V is already used in commercial SoCs and MCUs from companies such as [SiFive](https:\u002F\u002Fwww.sifive.com\u002F), [Andes Technology](https:\u002F\u002Fwww.andestech.com\u002F), [Espressif Systems](https:\u002F\u002Fwww.espressif.com\u002F), [StarFive](https:\u002F\u002Fwww.starfivetech.com\u002F), and [Raspberry Pi](https:\u002F\u002Fwww.raspberrypi.com\u002F). The architecture is also supported by several major Linux distributions, which makes it more practical for general-purpose computing.\u003C\u002Fp>\u003Cp>Performance claims vary widely across implementations, and that is normal for an ISA. The source notes one headline example from Micro Magic Inc. in October 2020: a 64-bit RISC-V core reported at 5 GHz and 13,000 CoreMarks. That kind of result shows how far the upper end of the ecosystem has moved.\u003C\u002Fp>\u003Cul>\u003Cli>Microcontrollers for low-power devices\u003C\u002Fli>\u003Cli>Embedded systems for appliances and industrial gear\u003C\u002Fli>\u003Cli>Higher-performance chips aimed at mobile, desktop, and server use\u003C\u002Fli>\u003C\u002Ful>\u003Ch2>5. The software and tooling story\u003C\u002Fh2>\u003Cp>A CPU architecture matters only if the software stack follows. RISC-V has compiler, operating system, and development-tool support, which is why it has moved beyond lab demos and into shipping hardware. The ecosystem also includes the RISC-V Software Ecosystem, or RISE, launched by the Linux Foundation Europe in 2023.\u003C\u002Fp>\u003Cp>RISE is meant to expand software availability for power-efficient and high-performance RISC-V processors. Its initial members include Red Hat, Samsung, Qualcomm, \u003Ca href=\"\u002Ftag\u002Fnvidia\">Nvidia\u003C\u002Fa>, MediaTek, Intel, and \u003Ca href=\"\u002Ftag\u002Fgoogle\">Google\u003C\u002Fa>, which signals broad industry interest in making the platform easier to use.\u003C\u002Fp>\u003Cul>\u003Cli>Compiler support for mainstream toolchains\u003C\u002Fli>\u003Cli>Linux support across multiple distributions\u003C\u002Fli>\u003Cli>Growing vendor participation in software enablement\u003C\u002Fli>\u003C\u002Ful>\u003Ch2>How to decide\u003C\u002Fh2>\u003Cp>If you want the simplest mental model, think of RISC-V as an open rulebook for building processors. If you are a hardware team, the open ISA and extension system give you room to tune cost, power, and performance. If you are a software or systems team, the growing toolchain and Linux support make it easier to treat RISC-V like a real deployment target.\u003C\u002Fp>\u003Cp>For readers comparing it with older proprietary ISA families, the main appeal is control: no royalties, public specs, and enough flexibility to scale from tiny MCUs to larger SoCs. That combination is what has made RISC-V a serious option across embedded and general-purpose computing.\u003C\u002Fp>","5 RISC-V basics explain the open ISA, its extensions, and why chips from MCUs to servers now use it.","en.wikipedia.org","https:\u002F\u002Fen.wikipedia.org\u002Fwiki\u002FRISC-V",null,"https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779361569517-1iaf.png","industry","en","cdc5718c-0992-4268-ae04-7d5bb207de6c",[17,18,19,20,21,22,23,24],"RISC-V","open ISA","instruction set architecture","embedded systems","SoCs","microcontrollers","Linux support","RISC-V International",[26,27,28],"RISC-V is an open, royalty-free instruction set architecture used across many chip types.","Its extension model lets designers add only the features they need.","The ecosystem now includes major companies, Linux support, and a broad tooling stack.",3,"2026-05-21T11:05:39.535169+00:00","2026-05-21T11:05:39.514+00:00","259fa19c-8d25-4dc5-97cb-6868f4befee8",{"tags":34,"relatedLang":11,"relatedPosts":45},[35,37,39,41,43],{"name":21,"slug":36},"socs",{"name":19,"slug":38},"instruction-set-architecture",{"name":17,"slug":40},"risc-v",{"name":18,"slug":42},"open-isa",{"name":20,"slug":44},"embedded-systems",[46,52,58,64,70,76],{"id":47,"slug":48,"title":49,"cover_image":50,"image_url":50,"created_at":51,"category":13},"47702da7-3093-408a-90aa-9f5f461ccce9","openai-ipo-filing-turns-hype-into-scrutiny-en","OpenAI’s IPO filing turns hype into scrutiny","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1781042611120-ynji.png","2026-06-09T22:03:05.09084+00:00",{"id":53,"slug":54,"title":55,"cover_image":56,"image_url":56,"created_at":57,"category":13},"619fab96-00b8-42f2-a3ff-13db32d6ac7b","skatteetaten-public-sector-ai-outcomes-en","Skatteetaten proves public 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