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It matters because it lowers licensing barriers and enables custom silicon for local AI, HPC, and embedded systems.",[12,21,28,36,43,50,57,64,72,79],{"id":13,"slug":14,"title":15,"summary":16,"category":17,"image_url":18,"cover_image":18,"language":19,"created_at":20},"5f8c17a6-6c8f-4db9-997e-24bbc6166716","hightec-sifive-safety-critical-risc-v-development-en","Why HighTec and SiFive are right to push safety-critical RISC-V","HighTec and SiFive are right: safety-critical automotive and industrial software needs qualified RISC-V toolchains, not more proprietary lock-in.","industry","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1778425846175-p0od.png","en","2026-05-10T15:10:25.064771+00:00",{"id":22,"slug":23,"title":24,"summary":25,"category":17,"image_url":26,"cover_image":26,"language":19,"created_at":27},"cff0f03f-8419-410d-a2f2-8b2e0b89a93e","why-banana-pi-risc-v-edge-ai-board-matters-en","Why Banana Pi’s RISC-V edge AI board matters","Banana Pi’s BPI-SM10 shows RISC-V is ready for serious local AI hardware.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1777969864596-qu0p.png","2026-05-05T08:30:37.056245+00:00",{"id":29,"slug":30,"title":31,"summary":32,"category":33,"image_url":34,"cover_image":34,"language":19,"created_at":35},"38bfb247-860f-4044-83ea-0964a269e2a1","banana-pi-bpi-sm10-risc-v-ai-sbc-en","Banana Pi’s BPI-SM10 targets local AI on RISC-V","Banana Pi’s BPI-SM10 pairs a RISC-V chip with up to 60 TOPS for local AI, plus USB 3.0, Gigabit Ethernet, and M.2 slots.","tools","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1777639252479-p6cz.png","2026-05-01T12:40:35.808767+00:00",{"id":37,"slug":38,"title":39,"summary":40,"category":17,"image_url":41,"cover_image":41,"language":19,"created_at":42},"c3a5c73d-8ac2-4f0d-8554-49a13919a5a6","calligo-raises-12-15-million-risc-v-chip-push-en","$12-15 million for Calligo’s RISC-V chip push","Calligo Technologies is seeking $12-15 million, led by BIG Capital, to scale its indigenous RISC-V chips for AI and HPC markets.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1777638652609-hxju.png","2026-05-01T12:30:31.514468+00:00",{"id":44,"slug":45,"title":46,"summary":47,"category":17,"image_url":48,"cover_image":48,"language":19,"created_at":49},"0b5b7804-ce6a-4fe1-92fd-fcbeef8f5f9d","canonical-ubuntu-risc-v-2026-desktop-server-en","Canonical Bets on Ubuntu for RISC-V in 2026","Canonical says 2026 will be the year RISC-V moves from pilots to commercial Ubuntu systems, including desktop and server hardware.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775272196612-525w.png","2026-04-04T03:09:33.125053+00:00",{"id":51,"slug":52,"title":53,"summary":54,"category":17,"image_url":55,"cover_image":55,"language":19,"created_at":56},"f9ee5b22-b62c-4941-868e-7722b84b554b","alibaba-risc-v-ai-cpu-server-chips-en","Alibaba’s RISC-V AI CPU Pushes Into Server Chips","Alibaba’s 64-bit RISC-V CPU hits 3.2 GHz on TSMC 5nm, targets agentic AI, and challenges Arm and Apple-style server silicon.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775197509113-we45.png","2026-04-03T06:24:45.325498+00:00",{"id":58,"slug":59,"title":60,"summary":61,"category":17,"image_url":62,"cover_image":62,"language":19,"created_at":63},"063ea8e9-ebc7-43ac-9f9e-061f5aaf52b9","china-riscv-achievements-open-source-chip-industry-en","China’s RISC-V push hits a new milestone","CAS says Xiangshan set a new record and Ruyi first supported RVA23, signaling a bigger push for open-source chips in China.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775180033405-nimr.png","2026-04-03T01:33:30.816685+00:00",{"id":65,"slug":66,"title":67,"summary":68,"category":69,"image_url":70,"cover_image":70,"language":19,"created_at":71},"0d7fb12b-52c1-476e-8d17-ae10816464d2","esp32-s31-wifi-6-gigabit-ethernet-risc-v-en","Espressif’s ESP32-S31 packs Wi‑Fi 6 and Gigabit Ethernet","Espressif’s ESP32-S31 pairs dual RISC-V cores with Wi‑Fi 6, Bluetooth 5.4, 802.15.4, and Gigabit Ethernet in a single MCU.","model-release","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775179847171-jz8q.png","2026-04-03T01:30:31.748018+00:00",{"id":73,"slug":74,"title":75,"summary":76,"category":33,"image_url":77,"cover_image":77,"language":19,"created_at":78},"6b09d971-3ca8-4e5e-a6fa-9c176b5b4892","rise-free-risc-v-github-runners-en","RISE Adds Free RISC-V GitHub Runners","RISE now offers free GitHub Runners on real RISC-V hardware, removing a major CI barrier for open source projects.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775179665803-38vj.png","2026-04-03T01:27:27.818832+00:00",{"id":80,"slug":81,"title":82,"summary":83,"category":17,"image_url":84,"cover_image":84,"language":19,"created_at":85},"ba4d8580-aa49-4ade-8016-578a12e7794f","rvcc-llvm-incubator-riscv-optimizations-en","RVCC Wants Faster RISC-V Tuning in LLVM","RVCC is being proposed as an LLVM incubator to speed up RISC-V compiler tuning, but LLVM maintainer Nikita Popov already objects.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775179487144-likv.png","2026-04-03T01:24:25.94061+00:00"]