Tag
RISC-V
RISC-V is an open instruction set architecture moving from hobby boards into AI SBCs, server-class chips, and mainstream Linux and Ubuntu support. It matters because it lowers licensing barriers and enables custom silicon for local AI, HPC, and embedded systems.
28 articles
RISC-V mini PCs are worth buying now, but only as a bet on the future
RISC-V mini PCs are not mainstream-ready, but they are finally worth buying as early proof of the architecture.
Fedora 44 RISC-V widens Linux board support
Fedora 44 RISC-V images add an Omni kernel that boots on 17 boards and broadens support beyond upstream-ready hardware.
How to Set Up a SpacemiT K3 RISC-V SBC
Set up a SpacemiT K3 Pico-ITX SBC or K3-CoM260 SoM for boot, storage, networking, and OS testing.
MIPS shows RISC-V AI IP for edge models at CES
MIPS unveiled S8200, a RISC-V AI processor IP block for edge models that targets tens to hundreds of TOPS and 2027 silicon.
How to use the Petros CH32H417M Alef board
Set up the Petros CH32H417M Alef as a Pico-sized RISC-V camera board.
Why RISC-V and GPU Pairing Is the Right SoC Bet
RISC-V SoCs win when they pair CPU, AI, and GPU into one software-ready platform.
RISC-V news turns chip tracking into a playbook
I break down EE Times’ RISC-V tag page into a practical watchlist for AI, sovereignty, and chip design moves.
5 reasons RISC-V is winning new chip designs
5 reasons RISC-V is moving from academia to standard status, as its CEO says it is becoming the default ISA for new chips.
Why ByteDance Is Right to Build Its Own CPUs
ByteDance should build in-house CPUs to control cost, supply, and AI infrastructure performance.
CEA-List’s RISC-V booth turns Summit into a playbook
CEA-List’s Summit page turns one event listing into a practical RISC-V meetup and demo plan.
Alibaba runs Android 16 on RISC-V chips
Alibaba’s DAMO Academy says it has ported Android 16 to XuanTie RISC-V silicon, a first for RVA23 processors.
5 reasons ByteDance is building custom CPUs
5 reasons ByteDance is building custom CPUs for AI data centers, from rising Intel and AMD prices to export controls and Arm vs RISC-V bets.
How to Evaluate Firefly CSC2-N48SPK3
Evaluate Firefly’s 48-node RISC-V AI server and its software fit before buying.
RISC-V router crowdfunding, E Ink kit, Windows 11 taskbar
Start9 is crowdfunding a $300 RISC-V Wi‑Fi router, M5Stack launched a $75 E Ink color dev kit, and Windows 11 taskbar tweaks are back for Insiders.
SingNova-H Studio turns local AI into a PC
SingNova-H Studio packs 200 TOPS into a local AI PC built around RISC-V dataflow design.
5 RISC-V basics for builders
5 RISC-V basics explain the open ISA, its extensions, and why chips from MCUs to servers now use it.
SiFive launches third-gen P550 and P570 cores
SiFive launched third-generation P550 and P570 RISC-V cores, led by the P570 Gen 3 out-of-order core for high-performance designs.
Why SiFive’s P570 Gen3 matters more as a platform than a core
SiFive’s P570 Gen3 is important because RVA23 support turns RISC-V into a serious mainstream platform.
Why HighTec and SiFive are right to push safety-critical RISC-V
HighTec and SiFive are right: safety-critical automotive and industrial software needs qualified RISC-V toolchains, not more proprietary lock-in.
Why Banana Pi’s RISC-V edge AI board matters
Banana Pi’s BPI-SM10 shows RISC-V is ready for serious local AI hardware.
Banana Pi BPI-SM10: RISC-V Board for Local AI
Banana Pi’s BPI-SM10 pairs a RISC-V chip with up to 60 TOPS for local AI, plus USB 3.0, Gigabit Ethernet, and M.2 slots.
$12-15 million for Calligo’s RISC-V chip push
Calligo Technologies is seeking $12-15 million, led by BIG Capital, to scale its indigenous RISC-V chips for AI and HPC markets.
Canonical Bets on Ubuntu for RISC-V in 2026
Canonical says 2026 will be the year RISC-V moves from pilots to commercial Ubuntu systems, including desktop and server hardware.
Alibaba’s RISC-V AI CPU Pushes Into Server Chips
Alibaba’s 64-bit RISC-V CPU hits 3.2 GHz on TSMC 5nm, targets agentic AI, and challenges Arm and Apple-style server silicon.
China’s RISC-V push hits a new milestone
CAS says Xiangshan set a new record and Ruyi first supported RVA23, signaling a bigger push for open-source chips in China.
Espressif’s ESP32-S31 packs Wi‑Fi 6 and Gigabit Ethernet
Espressif’s ESP32-S31 pairs dual RISC-V cores with Wi‑Fi 6, Bluetooth 5.4, 802.15.4, and Gigabit Ethernet in a single MCU.
RISE Adds Free RISC-V GitHub Runners
RISE now offers free GitHub Runners on real RISC-V hardware, removing a major CI barrier for open source projects.
RVCC Wants Faster RISC-V Tuning in LLVM
RVCC is being proposed as an LLVM incubator to speed up RISC-V compiler tuning, but LLVM maintainer Nikita Popov already objects.