SiFive launches third-gen P550 and P570 cores

SiFive launched third-generation P550 and P570 RISC-V cores for high-performance chip designs.

SiFive has pushed its RISC-V portfolio into a new generation with the Performance P550 and Performance P570 Gen 3 cores. The company says the new P570 Gen 3 is its most powerful and efficient out-of-order processor core in its class, aimed at designers who want higher-end CPU performance without leaving the RISC-V ecosystem.

That matters because RISC-V has moved well past hobbyist boards and academic demos. It now sits in the same conversation as ARM and x86 for serious compute blocks, and SiFive is trying to prove that open instruction-set silicon can compete in premium segments too.

What SiFive actually announced

The announcement is short on public technical detail, but the headline is clear: SiFive is refreshing its Performance family with third-generation IP. The company did not publish full benchmark data in the release excerpt, but the wording signals a focus on out-of-order execution, better efficiency, and stronger sustained performance for demanding workloads.

For chip teams, that kind of IP update matters more than marketing language. A new core generation can change power budgets, die area, cache planning, and how much headroom a design has for operating systems, AI inference, networking, or client-style workloads.

• The new cores are the P550 Gen 3 and P570 Gen 3.
• SiFive describes the P570 Gen 3 as its most powerful and efficient out-of-order core in its class.
• The launch came from SiFive in Santa Clara, California.
• The company positions the release as third-generation Performance IP for RISC-V computing.

Why this release matters for RISC-V

RISC-V adoption has always had a split personality. On one side, it is attractive because the instruction set is open and flexible. On the other, serious customers still ask whether it can match the performance and software maturity of entrenched architectures. SiFive keeps answering that question by moving up the stack, from embedded cores toward higher-performance CPU IP.

The P570 Gen 3 is especially important because out-of-order cores are where a lot of the hard engineering lives. These designs are more complex, more power-hungry, and more expensive to tune than simpler in-order cores. If SiFive can ship a competitive out-of-order core family, it gives chip vendors a stronger option for laptops, edge servers, automotive compute, and custom SoCs.

"RISC-V is the first open standard instruction set architecture that is not tied to a single company or country," said Krste Asanović, professor at UC Berkeley and a founder of the RISC-V project.

That quote gets to the core of the appeal. The value of RISC-V is not only technical; it is also strategic. Companies want more control over their CPU roadmaps, licensing costs, and long-term differentiation. SiFive is selling IP into that need.

How this compares with the market

SiFive is not the only company building on RISC-V, but it is one of the names most closely associated with commercial CPU IP. That gives the Performance family a special role: it is a proof point for whether RISC-V can scale into performance-sensitive products rather than staying in microcontrollers and niche accelerators.

Even without benchmark numbers in the release, the positioning tells a story. SiFive is not trying to win on openness alone. It is trying to win on performance per watt, integration flexibility, and the ability to drop a ready-made CPU block into a custom chip design.

• Arm still dominates mainstream mobile and many embedded designs.
• Intel and AMD still own the x86 PC and server center of gravity.
• SiFive is trying to make RISC-V a practical choice for high-end custom silicon.
• RISC-V International keeps expanding the ecosystem around the ISA.

That competition is healthy for chip buyers. More viable CPU options usually mean more negotiating power, more design freedom, and less dependence on a single vendor’s roadmap. For the broader industry, it also means RISC-V is no longer a side project. It is a serious platform with commercial pressure behind it.

What to watch next

The real test is not the announcement itself. It is whether SiFive publishes concrete performance, power, and area data, and whether customers actually tape out products with these cores. The next useful signal will be design wins, SDK support, and whether the P570 Gen 3 shows up in chips that need more than embedded-class performance.

If SiFive can pair this IP with strong software support and real silicon results, the P550 and P570 Gen 3 could become reference points for what high-performance RISC-V looks like in practice. The question now is simple: which chip vendor will be first to ship a product built around them?