Tag
RISC-V
RISC-V is an open instruction set architecture moving from hobby boards into AI SBCs, server-class chips, and mainstream Linux and Ubuntu support. It matters because it lowers licensing barriers and enables custom silicon for local AI, HPC, and embedded systems.
10 articles
Why HighTec and SiFive are right to push safety-critical RISC-V
HighTec and SiFive are right: safety-critical automotive and industrial software needs qualified RISC-V toolchains, not more proprietary lock-in.
Why Banana Pi’s RISC-V edge AI board matters
Banana Pi’s BPI-SM10 shows RISC-V is ready for serious local AI hardware.
Banana Pi’s BPI-SM10 targets local AI on RISC-V
Banana Pi’s BPI-SM10 pairs a RISC-V chip with up to 60 TOPS for local AI, plus USB 3.0, Gigabit Ethernet, and M.2 slots.
$12-15 million for Calligo’s RISC-V chip push
Calligo Technologies is seeking $12-15 million, led by BIG Capital, to scale its indigenous RISC-V chips for AI and HPC markets.
Canonical Bets on Ubuntu for RISC-V in 2026
Canonical says 2026 will be the year RISC-V moves from pilots to commercial Ubuntu systems, including desktop and server hardware.
Alibaba’s RISC-V AI CPU Pushes Into Server Chips
Alibaba’s 64-bit RISC-V CPU hits 3.2 GHz on TSMC 5nm, targets agentic AI, and challenges Arm and Apple-style server silicon.
China’s RISC-V push hits a new milestone
CAS says Xiangshan set a new record and Ruyi first supported RVA23, signaling a bigger push for open-source chips in China.
Espressif’s ESP32-S31 packs Wi‑Fi 6 and Gigabit Ethernet
Espressif’s ESP32-S31 pairs dual RISC-V cores with Wi‑Fi 6, Bluetooth 5.4, 802.15.4, and Gigabit Ethernet in a single MCU.
RISE Adds Free RISC-V GitHub Runners
RISE now offers free GitHub Runners on real RISC-V hardware, removing a major CI barrier for open source projects.
RVCC Wants Faster RISC-V Tuning in LLVM
RVCC is being proposed as an LLVM incubator to speed up RISC-V compiler tuning, but LLVM maintainer Nikita Popov already objects.