RISE Adds Free RISC-V GitHub Runners

RISC-V just got a practical boost: the RISC-V Software Ecosystem project, better known as RISE, has opened free GitHub Runners for open source teams. The pitch is simple and very specific: if your project lives on GitHub and targets riscv64, you can run CI on real hardware instead of relying on emulators or guessing.

That matters because RISC-V adoption has often been blocked by a boring but real problem: testing. Boards exist, but good boards cost money, and volunteer-led projects rarely have spare cash for a rack of them. RISE is trying to remove that friction by offering managed runners at no charge to open source projects.

What RISE is actually offering

RISE says the service gives GitHub projects access to physical RISC-V machines for continuous integration. In practice, that means a maintainer can point a workflow at a runner, install a GitHub App, and start testing on real silicon. No cross-compilation workarounds. No QEMU-only confidence. No waiting for a hardware lab slot.

The project’s own framing is worth paying attention to. Ludovic Henry, who is associated with the RISE announcement, described the service as an early availability release for a managed GitHub Actions runner service that gives open source projects access to real RISC-V hardware in CI pipelines.

For developers, the appeal is obvious. Build failures on an architecture you barely test are expensive to diagnose later, especially when a library or runtime gets used in embedded boards, SBCs, or server experiments. Catching those issues early is the whole point of CI, and RISC-V projects have often lacked the hardware to do that well.

• Service type: managed GitHub Actions runners
• Hardware access: physical RISC-V boards
• Cost: free for open source projects
• Primary use: build and test pipelines
• Platform support: GitHub only at launch

Why this matters for the RISC-V ecosystem

RISC-V has been around for more than a decade in public form, after years of work at the University of California, Berkeley. The ISA is open and permissively licensed, which is why it has attracted everyone from commercial chip vendors to hobbyist hardware builders. SiFive sells processor IP built around the architecture, while open hardware projects have used it in chips and microcontrollers too.

That openness is useful only if software keeps up. A chip architecture can look promising on paper, but if maintainers cannot test their code on real devices, the ecosystem slows down. RISE was created to help with exactly that gap, and these runners are a direct response to the hardware scarcity problem.

This is where the practical value gets interesting. Many open source projects can afford a few cloud instances, but not specialized hardware farms. RISC-V boards that are cheap enough for hobbyists often are not fast enough for serious CI, while faster boards can be expensive enough to scare off small teams. RISE is trying to sit in the middle and absorb that cost for the community.

• RISC-V public development began in 2014 after work at UC Berkeley
• The ISA is open and permissively licensed
• RISE is under the Linux Foundation
• The runner service is aimed at open source maintainers
• The service is currently tied to GitHub workflows

The hardware problem has been the real bottleneck

Software support for a new architecture usually fails for mundane reasons. Maintainers need repeatable test coverage, stable machines, and enough throughput to keep CI from becoming a bottleneck. RISC-V projects often had to choose between slow emulation and buying their own boards. Neither option is great when you are maintaining a widely used library.

RISE’s answer is to give open source teams access to hardware they probably would not buy themselves. That is a strong move because it changes RISC-V from a “nice to support” target into something that is easier to include in normal development workflows.

The service is also a reminder that architecture adoption is not just about silicon. Toolchains, libraries, package builds, and test automation matter just as much. If those pieces are hard to access, hardware progress stalls even when the chips themselves are ready.

“Today, we are excited to announce the Early Availability of the RISE RISC-V Runners, a free, managed GitHub Actions runner service that gives any open source project access to real RISC-V hardware in their CI pipelines,” said Ludovic Henry of RISE.

How it compares to the usual options

Most teams that want to validate RISC-V support have used one of four paths: emulation, cross-compilation, self-hosted boards, or shared lab resources. Each has tradeoffs, but the new runner service removes one of the most annoying ones: owning and maintaining the hardware yourself.

Here is the practical comparison, with the important differences spelled out.

• Emulation: cheap and easy to start, but it does not always reflect real hardware behavior or performance.
• Cross-compilation: useful for build validation, but it misses runtime bugs and hardware-specific failures.
• Self-hosted boards: accurate, but they require purchase, setup, power, maintenance, and replacement planning.
• RISE runners: real hardware, no direct hardware cost for open source projects, and much less infrastructure work for maintainers.

There is one catch worth noting. At launch, the service is available only through GitHub, so projects hosted elsewhere need to mirror or move if they want to use it. That makes the offer less universal than the headline suggests, but it still helps a huge slice of the open source world because GitHub remains where many infrastructure-heavy projects already live.

For maintainers, the real question is whether the service stays easy to use and well provisioned once more projects discover it. If it does, RISC-V could become much easier to support in the same way x86 and ARM are supported today: as a routine CI target, not a special case.

What happens next

RISE is doing something smart here. Instead of asking open source developers to care more about RISC-V, it is removing the cost and friction that kept them from testing it properly in the first place. That is the kind of infrastructure move that can quietly change adoption patterns over time.

My bet is that the first wins will come from libraries, compilers, and low-level tooling where architecture bugs show up fast and hurt everyone downstream. If the queue stays short and the hardware stays reliable, expect more projects to add riscv64 to their CI by default rather than as an afterthought. The bigger question is whether RISE expands beyond GitHub, because that would decide how far this service can reach.

For now, the takeaway is straightforward: if your open source project targets RISC-V, there is finally a free way to test on real boards without buying your own farm. That alone makes this announcement worth a serious look.

Related reading: how open hardware CI is changing embedded development.